The present invention is related to integrated circuit (IC) devices. More particularly, the present invention relates to a method of locally forming a specialized channel region for a transistor.
Transistors are generally formed on the top surface of a semiconductor substrate. Typically, the semiconductor substrate is divided into a number of active and isolation regions through an isolation process, such as field oxidation or shallow trench isolation (STI). A thin oxide is grown on an upper surface of the semiconductor substrate in the active regions. The thin oxide serves as the gate oxide for subsequently formed transistors.
Polysilicon gate conductors are formed in the active regions above the thin oxide. The gate conductor and thin oxide form a gate structure which traverses each active region, effectively dividing the active region into two regions referred to as a source region and a drain region. After formation of the polysilicon gates, an implant is performed to introduce an impurity distribution into the source/drain regions. Generally, source/drain regions are heavily doped with n-type or p-type dopants.
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-inducted barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region just below the top surface of the substrate to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. With the silicon dioxide spacers in place, the substrate is doped a second time to form deep source and drain regions. During formation of the deep source and drain regions, further doping of the source and drain extensions is inhibited due to the blocking characteristic of the silicon dioxide spacers. The deep source and drain regions are necessary to provide sufficient material to connect contacts to the source and drain regions.
As transistors become smaller, it is desirous to increase the charge carrier mobility in the channel region. Increasing charge carrier mobility increases the switching speed of the transistor. Channel regions formed from materials other than silicon have been proposed to increase charge carrier mobility. For example, conventional thin film transistors which typically utilize polysilicon channel regions have been formed on a silicon germanium (Sixe2x80x94Ge) epitaxial layer above a glass (SiO2) substrate. The Sixe2x80x94Ge epitaxial layer can be formed by a technique in which a semiconductor thin film, such as, an amorphous silicon hydride (a-Si:H), an amorphous germanium hydride (a-Ge:H) or the like is melted and crystallized by the irradiation of pulse laser beams.
In a bulk type device, such as, a metal oxide semiconductor field effect transistor (MOSFET), the use of Sixe2x80x94Ge materials can increase charge carrier mobility, especially hole type carriers. A channel region containing germanium can have charge carrier mobility 2-5 greater than a conventional Si channel region due to reduce charge carrier scattering and due to the reduced mass of holes in the germaniumcontaining material. According to conventional Sixe2x80x94Ge formation techniques for bulk-type devices, a dopant implanted molecular beam epitaxy (MBE) technique forms a Sixe2x80x94Ge epitaxial layer. However, the MBE technique requires very complicated, very expensive equipment and is not feasible for mass production of ICs.
A silicon germanium layer can be provided in the channel region to achieve a channel region containing germanium. As transistor dimensions are minimized, the thickness of the silicon germanium layer must be very thin (e.g., less than several hundred angstroms). Further, a very sharp interface between the silicon substrate and silicon germanium layer is required. Conventional fabrication methods have not been able to feasibly produce thin silicon germanium layers having an abrupt or very sharp interface in the silicon substrate.
Thus, there is a need for an integrated circuit or electronic device that includes channel regions with higher channel mobility. Further still, there is a need for transistors with a thin and abrupt Sixe2x80x94Ge channel layer. Even further still, there is a need for a method of manufacturing a transistor having a thin Sixe2x80x94Ge channel region on a bulk-type semiconductor substrate. Yet further still, there is a need for a method of fabricating a thin silicon-germanium channel layer with a very sharp interface between it and a silicon substrate.
An exemplary embodiment relates to a method of forming a channel region for a transistor. The method includes providing a layer of material over a gate structure above a substrate, and selectively creating an aperture in the layer of material. A sacrificial gate material is exposed when the aperture is created. The method further comprises removing the sacrificial gate material to leave the recess and providing a semiconductor implant through the recess to the channel region.
Another exemplary embodiment relates to a method of forming a transistor. The method includes steps of: depositing a layer of material over a gate structure, polishing the layer of the material over the gate structure, etching a sacrificial gate material to leave a recess, and implanting germanium ions into a substrate though the recess. The gate structure includes the sacrificial gate material. The polishing step is utilized to expose the sacrificial gate material. Etching the sacrificial gate material leaves the recess through which the germanium ions form a channel region including germanium.
Another exemplary embodiment relates to a method of forming an integrated circuit. The method includes providing a transistor above a substrate. The transistor includes a sacrificial gate material between a source region and a drain region. The method also includes providing an oxide liner over the sacrificial gate material, selectively removing the oxide liner to expose the sacrificial gate material, removing the sacrificial gate material, and doping the channel region to form the silicon germanium layer in the substrate.